1. Field of the Invention
The invention relates to an Electrically Erasable Programmable Read-Only Memory (EEPROM), and more specifically, to structures and methods for enabling multiple threshold voltage operation in single EEPROM cell.
2. Description of the Prior Art
Semiconductor non-volatile memory (NVM), and particularly electrically erasable, programmable read-only memory (EEPROM), is used in a range of electronic equipment from computers, to telecommunications hardware, to consumer appliances, and to subscriber identity modules (SIMs) for mobile phones. In general, EEPROMs serve a niche in the NVM space as a mechanism for storing firmware and data that can be kept even with power off and yet can be altered as needed. The flash EEPROM may be regarded as a specifically configured EEPROM that may be erased only on a global or sector-by-sector basis.
As is well known to those skilled in the art and as shown in FIGS. 1a˜1e and 2a˜2e, EEPROM cells with drain/source regions 1a, 1b, 1d, 1g, 13c, 13f and 2a, 2b, 2d, 2g, 9c, 9f, formed by ion implantation, are typically constructed by forming a field effect transistor (FET) in a body of semiconductor material (such as P-substrate or P-well 1e, 1c, 3d or N-substrate or N-well 1f, 2f, 3f), usually silicon. In one configuration, shown in FIGS. 1a and 2a, the FET can be made to store electrical charge in an insulated polysilicon gate electrode 4a or 4b, referred to as a floating gate 4a or 4b, separated from the underlying substrate 1e or 1f and the drain/source regions 1a and 2a or 1b and 2b by bottom oxide layer 3a or 3b and from an overlying gate conductor 6a or 6b by a top oxide layer 5a or 5b. Besides this typical cell architecture, there are also varieties of device cells. For example, in the semiconductor-oxide-nitride-oxide-semiconductor (SONOS) NVM cell architecture, shown in FIG. 1b (2b)(hereinafter, to eliminate redundancy, the numbers in parentheses refer to the elements in the Figure the number of which is in parenthesis), the gate structure includes an oxide layer 7a (7b), a nitride layer 8a (8b) and an oxide layer 9a (9b) which together formed an oxide-nitride-oxide (ONO) dielectric stack. Charges are stored in the nitride layer 8a (8b) that is separated from the silicon substrate 1e (1f) by a bottom oxide layer 7a (7b) and from a poly-silicon gate conductor 6a (6b) by a top oxide layer 9a (9b). As shown in FIG. 1c (2c), the NVM cell is fabricated on a layer of isolated polycrystalline storage islands (made of polycrystalline particles) 10a (10b) that is formed underneath a control poly-silicon gate electrode 6a (6b).
The single-poly NVM cell architecture shown in FIG. 1d (2d) applies poly-silicon on top of the silicon substrate or well inside silicon substrate 1c (2f) to form a single poly-silicon floating gate 11a (11b) and control gate 12a (12b) respectively, (folded control gate electrode 10c (10f)).
The structure of a split-gate NVM shown in FIG. 1e (2e) uses poly-silicon on a silicon substrate (well) 3d (3f) to form a polysilicon floating gate 13a (13b), a control gate 14a (14b) separated from the polysilicon floating gate 13a (13b) by control dielectric 15a (15b) and tunneling dielectric 16a (16b) between the floating gate 13a (13b) and the underlying substrate or well 3d (3f).
Data is stored in an EEPROM cell by modulating the threshold voltage, Vth, of the FET through the injection of charge carriers into the charge-storage layer from the channel of the FET. For example, with respect to an N channel FET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the FET to exhibit a relatively high positive Vth. When the FET control gate is biased to the voltage required to read stored data, the FET, with a fixed drain voltage, will respond with different source-to-drain currents according to its Vth level. The different source-to-drain current responses can be recognized and converted to the original bit information stored on the charge storage layer of the FET.
The number of bits stored in an EEPROM cell is determined by the number of different current responses, given by number-of-bits=log2 (number of current responses). The more different current responses that can be sensed and resolved, the more bits that can be stored in a single device cell. In modem sense amplifier (SA) design, the current can be measured with very high accuracy and speed. Usually reference cells are used to compare the current response and determines the bit-level information. However, the major challenge to achieving multi-bit storage in a single device cell is to accurately program or erase the charge-storage layer so as to achieve a designated threshold voltage level which results in a consistent device current response under the read operation.
In the conventional write and erase schemes, Drain-Avalanche-Hot Carrier Injection (DAHCI) and Fowler-Nordheim Tunneling (FNT) have been used for programming and erasing, respectively. The amount of charge injected into/out of the floating gate is controlled by the DAHCI/FNT currents generated by applying voltage pulses to the device gate and electrodes (source, drain, and substrate). Since there is no self-convergent mechanism for DAHCI programming and FNT erasing, the amount of charge in the floating gate which controls and determines the device threshold voltage shift is controlled by the durations of the voltage pulses applied to the gate and to the electrodes. Due to non-uniformity of distributed voltage supply across an integrated circuit memory and the RC time constant delay for a given voltage to reach individual devices in a memory array, the threshold voltage shifts associated with the devices in a memory array after conventional programming and erasing, are usually widely spread out. This hinders multiple-level recognition in a large number of cells in an array memory. To reduce such threshold voltage shift variations, an extra convergent circuit is usually supplied to fine-tune the desired threshold voltage level for each individual device cell in an EEPROM memory array. However, such an approach not only requires a complicated convergence circuit with more silicon area but also requires lengthy and time-consuming convergent procedures during programming.
In view of the aforementioned, the present invention provides an innovative scheme to achieve multiple-bit storage in electrically erasable programmable read-only memories (EEPROMs) to overcome the above drawbacks.